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as3931 3d low power wakeup receiver www.austriamicrosystems.com/as3931 revision 6.2 1 - 30 datasheet 1 general description the as3931 is an ultra low power, three channel lf ask receiver designed to operate in various applications such as lf identifications systems and lf tag receivers. as3931 detects a low frequency ask-modulated signal by looking for a digital wakeup pattern and generates a wake signal after succ essful pattern detection. the device incorporates an intelligent pattern detection algorithm that provides reliable operation in presence of strong interference. an rssi signal can be generated at the rssi pin for each receiver channel. the product is available in 16-pin tssop package. the as3931 contains: antenna rotation switch three independent lf receiver chains wakeup output combining the three receiver chains low power 32.768khz crystal oscillator circuit serial programming interface voltage regulator with 2.4v output, on/off switchable each independent lf receiver chain contains: input overload protection input attenuator ultra low power lf amplifier with logarithmic envelope output robust data detector with adaptive slicing threshold that translates the logarithmic envelope into a digital data signal. error tolerant digital pattern correlator that detects a given code sequences in the received data signal and generates a wakeup signal. sophisticated power management logic that powers down the correlator if no data is received. 2 key features programmable serial data interface flexible carrier frequencies three axis wakeup pattern detection three axis lf field strength measurement antenna rotation for easy calibration high sensitivity and high dynamic range wide operating frequency range reliable, interference resistant wakeup decoding highly protected differential inputs ultra low powe r consumption automotive qualified 16-pin tssop package 3 applications the device is ideal for lf identification systems, lf tag receivers, three dimensional lf field strength measurement systems, and ultra low power wake up systems. transmitting antenna receiving antennas v cc c bat r p c reg rssi data clock chip sel wake c b xtal c a vcc lf1n lf1p lf2n lf2p lf3n lf3p gnd xin xout wake cs scl sda rssi vreg as3931 figure 1. typical application diagram ams ag technical content still valid
www.austriamicrosystems.com/as3931 revision 6.2 2 - 30 as3931 datasheet - contents contents 1 general description .................................................................................................................................................................. 1 2 key features ............................................................................................................................................................................ 1 3 applications .............................................................................................................................................................................. 1 4 pin assignments ....................................................................................................................................................................... 4 4.1 pin descriptions ................................................................................................................................................................................... 4 5 absolute maximum ratings ...................................................................................................................................................... 5 6 electrical characteristics .......................................................................................................................................................... 6 7 typical operating characteristics ............................................................................................................................................. 9 7.1 rssi characteristic .............................................................................................................................................................................. 9 7.2 temperature dependence of rssi .................................................................................................................................................... 10 7.3 supply voltage dependence of rssi ................................................................................................................................................ 11 7.4 frequency dependence of rssi ....................................................................................................................................................... 12 8 detailed description ............................................................................................................................................................... 13 8.1 block diagram .................................................................................................................................................................................... 13 8.2 block description ............................................................................................................................................................................... 13 8.2.1 antenna rotator ........................................................................................................ ....... ...... .................................................... 13 8.2.2 input attenuator ....................................................................................................... .................................................................. 13 8.2.3 input shortcutting ..................................................................................................... .................................................................. 13 8.2.4 input protection circuit ............................................................................................... ............................................................... 13 8.2.5 logarithmic envelope amplifiers ........................................................................................ ....................................................... 14 8.2.6 detectors .............................................................................................................. ..................................................................... 14 8.2.7 digital correlators .................................................................................................... .................................................................. 14 8.2.8 wake generator ......................................................................................................... ............................................................... 14 8.2.9 crystal oscillator ..................................................................................................... ................................................................... 14 8.2.10 regulator ............................................................................................................. .................................................................... 14 8.2.11 power on reset (por) .................................................................................................. ......................................................... 14 8.3 basic operation .................................................................................................................................................................................. 15 8.3.1 lf transmission protocol ............................................................................................... . ...... .................................................... 15 8.3.2 wake up detection ...................................................................................................... .............................................................. 16 8.3.3 wake signal clearing ................................................................................................... ............................................................ 16 8.3.4 wake signal after por ............................................................................................................................................................ 16 8.3.5 rssi operation ......................................................................................................... ................................................................. 16 8.4 serial programming interface timing ................................................................................................................................................. 16 8.5 input signal waveform definition ....................................................................................................................................................... 17 9 configuring the product .......................................................................................................................................................... 18 9.1 serial programming interface ............................................................................................................................................................ 18 9.2 power on register ............................................................................................................................................................................. 18 9.2.1 p0, p1, p2 (channel enable) ............................................................................................ ..... ....... ............................................. 19 9.2.2 p3 (regulator enable) .................................................................................................. ............................................................. 19 9.2.3 p4, p5 (antenna rotator/input shortcut) ................................................................................................................................... 19 9.3 rssi channel select register ........................................................................................................................................................... 19 9.3.1 c0, c1 (rssi channel select) .............................................................................................. ....... ............................................. 20 9.3.2 c2, c3 (rssi output mode) .............................................................................................. ........................................................ 20 9.3.3 c4 (channel attenuator) ................................................................................................ ............................................................ 20 9.3.4 c5 (wake clear) ........................................................................................................ ............................................................... 21 ams ag technical content still valid
www.austriamicrosystems.com/as3931 revision 6.2 3 - 30 as3931 datasheet - contents 9.4 test mode register ............................................................................................................................................................................ 21 9.4.1 t0 (test mode enable) .................................................................................................. ........ .................................................... 21 9.4.2 t1, t2 (test mode select) .............................................................................................. ........................................................... 21 9.4.3 t3 ..................................................................................................................... .......................................................................... 22 9.4.4 t4 (rssi step select) ............................................................................................................................................................... 22 9.4.5 t5 (wake generator on/off) ..................................................................................................................................................... 22 9.5 correlator mode register ................................................................................................................................................................... 22 9.5.1 m0 (correlator off) ........................................................................................................... ...... .................................................... 23 9.5.2 m1 (single/double wake pattern) ........................................................................................ ..................................................... 23 9.5.3 m2, m3 (zero-half-bit detection mode) .................................................................................. ................................................... 23 9.5.4 m4 (detector time constant) ............................................................................................ ........................................................ 23 9.5.5 m5 ..................................................................................................................... ......................................................................... 23 10 extended operation .............................................................................................................................................................. 24 10.1 power management ......................................................................................................................................................................... 24 10.1.1 sleep mode ............................................................................................................ . ....... .......................................................... 24 10.1.2 standby mode .......................................................................................................... ................................................................ 24 10.1.3 receive mode .......................................................................................................... ................................................................ 24 10.1.4 regulator on/off ...................................................................................................... ................................................................ 24 10.1.5 typical current consumption in different modes ........................................................................ ............................................ 24 10.1.6 rssi step ................................................................................................................................................................................ 24 10.1.7 antenna rotation ...................................................................................................... ............................................................... 24 10.2 input attenuation and input shortcutting .......................................................................................................................................... 24 10.3 wake signal at the rssi pin .......................................................................................................................................................... 25 10.4 single wake operation ................................................................................................................................................................... 25 10.5 using the wake generator ............................................................................................................................................................... 25 10.6 direct data mode ............................................................................................................................................................................ 26 10.7 correlator modes ............................................................................................................................................................................. 26 10.8 threshold adaptation filter time constant ...................................................................................................................................... 26 10.9 rssi and wake pin modes ............................................................................................................................................................ 26 11 package drawings and markings ......................................................................................................................................... 27 12 ordering information ............................................................................................................................................................. 29 ams ag technical content still valid
www.austriamicrosystems.com/as3931 revision 6.2 4 - 30 as3931 datasheet - pin assignments 4 pin assignments figure 2. pin assignment s 16-pin tssop package 4.1 pin descriptions table 1. pin descriptions pin name pin number pin type description v cc 1 supply input positive supply voltage lf1n 2 analog input channel 1 negative input lf1p 3 analog input channel 1 positive input lf2n 4 analog input channel 2 negative input lf2p 5 analog input channel 2 positive input lf3n 6 analog input channel 3 negative input lf3p 7 analog input channel 3 positive input gnd 8 ground negative supply voltage xin 9 analog input crystal oscillator pin 1 xout 10 analog output crystal oscillator pin 2 wake 11 open drain wake up detect output/reset output cs 12 digital input with pulldown chip select scl 13 digital input with pulldown serial clock sda 14 digital input with pulldown serial data rssi 15 analog/digital output received signal strength indicator signal/ digital test mode signal output vreg 16 analog output regulator output voltage as3931 1 2 3 4 5 6 7 12 16 15 14 13 lf1n lf1p lf2n lf2p lf3n lf3p rssi sda scl cs wake xout 11 10 v cc vreg 8 9 gnd xin ams ag technical content still valid
www.austriamicrosystems.com/as3931 revision 6.2 5 - 30 as3931 datasheet - absolute maximum ratings 5 absolute maximum ratings stresses beyond those listed in table 2 may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions beyond those indicated in section 6 electrical characteristics on page 6 is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 2. absolute maximum ratings parameter min max units notes positive supply voltage (v cc ) -0.5 5.5 v analog ground (gnd) 00v voltage at any pin except pin 2 to pin 7 (v in )gnd-0.5 v cc +0.5 v voltage at pin 2 to pin 7 (v in ) gnd-0.5 gnd+0.5 v input current (latchup immunity) (i in ) -100 +100 ma jedec 78 electrostatic discharge (v esd ) 1000 v norm: mil 883 e method 3015 hbm: r=1.5 k , c=100 pf total power dissipation (p tot ) 300 mw storage temperature (t stg ) -55 125 oc package body temperature (t body ) +260 oc the reflow peak soldering temperature (body temperature) specified is in accordance with ipc/ jedec j-std-020 ?moisture/reflow sensitivity classification for non-hermetic solid state surface mount devices?. the lead finish for pb-free leaded packages is matte tin (100% sn). humidity non-condensing 5 85 % moisture sensitive level 3 represents a maximum floor life time of 168h operating ambient temperature range (t amb ) -20 +65 oc recommended operating conditions positive supply voltage (v cc ) 2.6 5.5 v regulator used positive supply voltage (v cc ) 2.4 3.5 v regulator not used analog ground (gnd) 00v ams ag technical content still valid
www.austriamicrosystems.com/as3931 revision 6.2 6 - 30 as3931 datasheet - electrical characteristics 6 electrical characteristics t amb = -20 to +65 c, v cc = 3.0 v, f in = 20 khz, register settings as after por, cs = low, transmission protocol according to figure 15 , figure 16 and application circuit according to figure 1 unless otherwise specified. table 3. electrical characteristics symbol parameter conditions min typ max units general f in lf input carrier frequency range 19 150 khz b r half-bit rate 1 2.704 2.731 2.758 kb/s b m manchester bit rate 2 1.352 1.365 1.379 kb/s w manchester code word 3 96 hex n pre preamble half-bits 4 8 v reg regulator voltage 5 v cc = 2.6 v to 5.5 v 2.30 2.4 2.60 v t por power on reset time 6 v cc = 2.4 v to 5.5 v 5 ms i cc operating current regulator off, v cc = 2.4 v; t amb = 27 c sleep mode 0.3 a standby mode 6.5 a receive mode 6.7 a regulator off, v cc = 2.4v to 3.5v; t amb = 27 c sleep mode 0.5 standby mode 6.8 regulator on, t amb = 27 c sleep mode 0.8 1.5 a standby mode 7.0 8.8 a receive mode 7.2 9 a regulator on, rssi-step = low; t amb = 27 c standby mode 6.6 i buf rssi buffer operating current 7 no load at rssi-pin 2 a v cc v cc transient compliance 8 recovery time = 10 ms; regulator on 8 , 2.6 v < v cc < 5.5 v for v cc after step 2v recovery time = 10 ms; regulator off 8 ; 2.4 v < v cc < 5.5 v for v cc before step 0.3 v z in differential small sig. input impedance normal operation; t amb = 27o 2 m input attenuator active; t amb = 27o 1.5 k input shortcutting active; t amb = 27o 0.5 k f xtal crystal oscillator frequency crystal type: cc4 from microcrystal 9 32.768 khz ams ag technical content still valid
www.austriamicrosystems.com revision 6.2 7 - 30 as3931 datasheet - electrical characteristics wakeup v in,min minimum differential input voltage for wake up detection 10 n pre = 8 t rise ,t fall < 150 s; v reg = 2.4 v to 3.5 v 11 350 vpp v in,max maximum differential input voltage for wake up detection 10 1vpp i wake wake pin current voltage at wake pin: v ol < 0.4 v; v reg = 2.4 v to 3.5 v 11 0.33 ma rssi v rssi rssi output voltage range 0.5 1.7 v v rssi0 rssi output voltage (rssi offset) v in = 0; 0.5 0.76 1.2 v v step rssi output voltage step 12 v in = 1 mv pp ; 100 290 mv v log logarithmic input voltage range v in = 1 mv pp , rssi step = high 0.3 300 mv s rssi rssi slope in log. range rssi step = high 12 mv/db c rssi cap. loading of rssi pin rssi buffer active 10 pf i rssi rssi buffer output current 5 a t step rssi voltage step time 13 c l = 10 pf, r l = 1 m ; input signal amplitude 100 mvpp; cs from low to high (buffer activation in presence of a strong input signal); 350 s channel switching from cha(100 mvpp) to chb (0 mvpp) 14 , with cs deactivation of 10 s 350 s v rip rssi ripple voltage rssi buffer active, c l = 10 pf, r l = 1 m ; v in = 1 mv pp ; 70 mv serial programming interface v il digital input l level pins scl, sda, cs; v reg = 2.4 v to 3.5 v 11 0.3 * v reg 11 v v ih digital input h level pins scl, sda, cs v reg = 2.4 v to 3.5 v 11 0.7 * v reg 11 v i ih digital input current pins scl, sda, cs v ih = 2.4 v; v reg = 2.4 v to 3.5 v 11 30 60 100 a tclk clock period v reg = 2.4 v to 3.5 v 11 2 s tch clock high duration v reg = 2.4 v to 3.5 v 11 500 ns tcl clock low duration v reg = 2.4 v to 3.5 v 11 500 ns table 3. electrical characteristics symbol parameter conditions min typ max units ams ag technical content still valid
www.austriamicrosystems.com revision 6.2 8 - 30 as3931 datasheet - electrical characteristics tdvch data valid to pos. clock edge v reg = 2.4 v to 3.5 v 11 100 ns tchdi pos. clock edge to data invalid v reg = 2.4 v to 3.5 v 11 100 ns tshch select active to pos. clock edge v reg = 2.4 v to 3.5 v 11 100 ns tchsl pos. clock to select inactive v reg = 2.4 v to 3.5 v 11 100 ns tsl select low time v reg = 2.4 v to 3.5 v 11 500 ns 1. the half-bit rate correlates with the crystal oscillator clock frequency f clk as follows: b r = f clk /12 2. the manchester bit rate correlates wi th the half-bit rate as follows: b m = b r /2 3. code word can be changed by metal option 4. 8 preamble half-bits are equivalent to 4 manchester bits 5. vreg output may not be used as a supply for other circuits 6. this is the internal power on reset time generated by the chip. to ensure proper start-up conditions, the supply voltage vcc must be ramped up to its final value during tpor 7. this is the additional operating current when the rssi buffer is activated without load 8. v cc means a hard step of the supply voltage down to a lower value by an amount of v cc ; after such a step, the analog circuits in the chip take some time to recover for working properly again. the maximum step value is listed. 9. crystal tolerance: 100ppm 10.values refer to production test 11.if regulator is on, then v reg = 2.4 v; if regulator is off, then v reg = v cc , where v cc = 2.4 v to 3.5 v 12.the rssi step is the change of the rssi output voltage when the input signal amplitude changes from 0 to specified value 13.time to step from initial rssi value to 95% of the final value 14.cha may be any channel 1 ? 3, whereas chb may be any other remaining channel. table 3. electrical characteristics symbol parameter conditions min typ max units ams ag technical content still valid
www.austriamicrosystems.com/as3931 revision 6.2 9 - 30 as3931 datasheet - typical operating characteristics 7 typical operating characteristics all graphs refer to tab = 27c and vreg = 2.4 v, unless otherwise stated. 7.1 rssi characteristic figure 3. rssi-characteristic vrssi [v] vs vin [vpp] 1.70 1.60 1.50 1.40 1.30 1.20 1.10 1.00 900m 800m 100 1m 10m 100m 1 ams ag technical content still valid
www.austriamicrosystems.com/as3931 revision 6.2 10 - 30 as3931 datasheet - typical operating characteristics 7.2 temperature dependence of rssi figure 4. rssi-step [v] @ vin = 1 mvpp and 2 mv figure 5. rssi-step [v] @ vin = 300 vpp and offset vs temp [deg c] vs. temp [deg c] figure 6. rssi-step [v] @ vin = 1 mv and 2 mv vs. figure 7. rssi-step [v] @ vin=300 vpp and offset temp [deg c], reduced step vs. temp [deg c], reduced step 410m 390m 370m 350m 330m 310m 290m 270m 250m 230m 210m -20 -10 0.0 10 20 temp 30 40 50 60 70 920m 900m 880m 860m 840m 820m 800m 70.0m 69.0m 68.0m 67.0m 66.0m 65.0m -20-100.010203040506070 1.020 1.010 1.000 990.0m 980.0m 970.0m 960.0m 950.0m 45.0m 44.0m 43.0m 42.0m -20 -10 0.0 10 20 30 40 50 60 70 v in = 300 v pp v in = 0 (offset) 290m 270m 250m 230m 210m 190m 170m 150m -20 -10 0.0 10 20 temp 30 40 50 60 70 ams ag technical content still valid
www.austriamicrosystems.com/as3931 revision 6.2 11 - 30 as3931 datasheet - typical operating characteristics 7.3 supply voltage dependence of rssi figure 8. rssi-step [v] @ vin = 1 mvpp and 2 mv fi gure 9. rssi-step [v] @ vin = 300 vpp and offset vs. vcc [v] vs. vcc [v] figure 10. rssi-step [v] @ vin = 1 mvpp and 2 mv vs figure 11. rssi-step [v] @ vin =300 vpp and offset vcc [v], reduced stepvs. vcc [v], reduced step 410m 390m 370m 350m 330m 310m 290m 270m 250m 2.40 2.60 2.80 3.00 3.20 3.40 3.60 87.0m 83.0m 79.0m 75.0m 71.0m 67.0m 2.00m 1.80m 1.60m 1.40m 1.20m 1.00m 800m 2.40 2.60 2.80 3.00 3.20 3.40 3.60 280m 260m 240m 220m 200m 180m 160m 2.40 2.60 2.80 3.00 3.20 3.40 3.60 57.0m 55.0m 53.0m 51.0m 49.0m 47.0m 45.0m 43.0m 2.10 1.90 1.70 1.50 1.30 1.10 900m 2.40 2.60 2.80 3.00 3.20 3.40 3.60 ams ag technical content still valid
www.austriamicrosystems.com/as3931 revision 6.2 12 - 30 as3931 datasheet - typical operating characteristics 7.4 frequency dependence of rssi figure 12. rssi-step [v] @ vin = 1 mvpp vs. fin [hz], rssi high step and low step 280m 260m 240m 220m 200m 180m 160m 140m 120m 100m 80.0m 10.k 100.k 1m ams ag technical content still valid
www.austriamicrosystems.com/as3931 revision 6.2 13 - 30 as3931 datasheet - detailed description 8 detailed description 8.1 block diagram figure 13. block diagram 8.2 block description 8.2.1 antenna rotator in order to achieve an optimum assignment of the antennas to the receiving channels, the connection of the antennas to the chan nels can be changed cyclically with a multiplexed (antenna rotator), which is controlled by an internal register. the register setting can be changed by the serial interface. 8.2.2 input attenuator input signal attenuation is provided for each channel by means of connecting a 1.5 k resistor across the differential inputs. an internal register control s attenuation. 8.2.3 input shortcutting the differential inputs can be shortened by register settings to measure the rssi offset. in this case, the resistance between the differential inputs is reduced to approximately 500 . 8.2.4 input protection circuit each signal input has a powerful input overload protection circuit consisting of two anti-parallel protection diodes connected to ground (see figure 14) . this connection ensures that the differential input voltage can never exceed the supply voltage of the chip. to obtain proper operation, the differential input receiving circuits (resonant rlc-circuits) must be floating and shall be grounded nowhere (see figure 1) lf1p lf1n lf2p lf2n lf3p lf3n cs scl sda vcc gnd v reg xin xout rssi wake input protection1 input protection2 input protection3 antenna rota- tor input attenuator1 input attenuator2 input attenuator3 log. env. amp 1 log. env. amp 2 log. env. amp 3 rssi1 rssi2 rssi3 detector1 detector2 detector3 rssi multiplexer control logic regulator regulator por rssi buffer data multiplexer wake generator correlator3 correlator2 correlator1 data1 data2 data3 wake1 wake2 wake3 wake multiplexer multiplexer as3931 ams ag technical content still valid
www.austriamicrosystems.com/as3931 revision 6.2 14 - 30 as3931 datasheet - detailed description figure 14. input protection circuit 8.2.5 logarithmic envelope amplifiers the logarithmic envelope amplifie rs amplify the ask coded lf inpu t signals. they generate received signal strength indicator (r ssi) signals, which are proportional to the logarithm of the received field strengths within the specified dynamic range. these signals are u sed for data detection and distance measurements. the rssi signals are bandwidth limited to reduce noise influence. the slope of the amplifi ers in the low signal range can be controlled by register settings: a high slope for increased sensitivity but also increased current consumpt ion and a weak slope with reduced current consumption are possible. 8.2.6 detectors the detectors convert the logarithmic envelope signal containing ask coded data into digital signals. each detector consists of a lowpass filter for generation of an adaptive threshold and a slicing comparator. a preamble is required for a proper adaptation of the thresho ld prior to the decision of the first valid data bit. a constant positive threshold offset is included in the comparator to ensure no data outp ut in case of no input signal. this increases the overall system noise immunity. 8.2.7 digital correlators the as3931 uses a 16-bit digital wakeup pattern. digital correlators perform the identification of this pattern. they use a sop histicated detection algorithm that provides high immunity against noise injection as a result of stochastic and periodic interference?s. the as3931 provides the possibility to double the length of the wake pattern to 32 bit. this is useful in environments with high noise levels to reduce the possibility of spurious (parasitic ) wakeups. in this case the usual wake pattern must be sent twice befor e a wake up is recognized and a wake signal is generated. this active low wake signal is generated afte r successful pattern i dentification. otherwise wake is high. setting a register bit via the serial-programming interface resets the correlators. in order to save power the correlators are stopped when no data has been r eceived for a specified amount of time. the correlators can be configured regarding their error tolerance by register settings. 8.2.8 wake generator a counter, clocked by the 32 khz crystal oscillator, generates an artificial wake up app. every 2 hours. this wake up can be us ed to manage the quiescent current consumption of the as3931. the idea behind is, to switch off one or more of the receiving channels in case of no true wake up detection for long times; that is when only parasitic wakeups or no wakeup at all is detected. an external controlling unit (c ) can identify this case by counting the parasitic wake ups and powering down one or more of the receiver channels to save current. when no wake up s are detected at all, e.g. if the application device is stored in a stock, then the wake generator?s artificial parasitic wakeups (e very 2 hours) can be used to identify the situation. 8.2.9 crystal oscillator the crystal oscillator generates the clock signal for the digital correlators. it has been optimized for a 32.768 khz quartz cr ystal connected to pins xin and xout. the oscillator provides extremely low current consumption, so it can be operated permanently by a battery. 8.2.10 regulator a regulator is implemented to provide the amplifiers and digital circuits with a stable and clean supply. the regulator can be switched off; in this case the external supply voltage is bypassed to the amplifiers and digital circuits. the regulator shall always be used for external supply voltages higher then 3.3v, otherwise the current consumption is significantly increased. the regulated voltage can be seen at the vreg p in, but may not be used to supply any other external circuits. 8.2.11 power on reset (por) a power on reset circuit guarantees proper circuit operation after pow er supply starts up. all internal registers are reset to their default states after power on. after the power on reset time, the active low wake output is activated and set to low (power on wake up). during the power on reset time, the wake output pi n is set to high. by this, it is ensured that this triggers the power on wake up triggered onl y when the internal registers are reset and ready to be programmed. lfn lfp gnd ams ag technical content still valid
www.austriamicrosystems.com/as3931 revision 6.2 15 - 30 as3931 datasheet - detailed description 8.3 basic operation 8.3.1 lf transmission protocol 8.3.1.1 data pattern the as3931 identifies a 16 half-bit binary coded data pattern, wh ich is ask-modulated on a lf carrier. the pattern must contain 8 logic 0 half- bits and 8 logic 1 half-bits in order to be dc free. furthermore, for a proper detector threshold adaptation it has to be ensur ed that there are no long groups of logic 0 and logic 1 half-bits. therefore coding of the 16 half-bit binary data to 8 manchester bits is common. t his means that 8 consecutive half-bit pairs are grouped to manchester bits whereas a manchester bit 1 is a high to low transition and a manche ster bit 0 is a low to high transition. the as3931 supports the manchester bit pattern 96 [hex] which in binary code is: 10 01 01 10 01 10 10 0 1. msb is transmitted first. the manchester bit pattern i.e. the binary data pattern can be changed on demand by a metal mask modificatio n. 8.3.1.2 double data pattern to increase the immunity against parasitic wakeups, the data pattern necessary for a successful wakeup can be doubled by progra mming the as3931: if the double data pattern is used, the pattern 96 has to be sent twice; after recognition of the first data pattern, t he second data pattern has to be sent immediately after the first one, otherwise no wake signal is generated. for the timing see wake up frame on page 15 . setting the bit m1 to 1 can program the double data pattern feature. 8.3.1.3 wake up frame the wake up frame of as3931 consists of a preamble used for detector threshold adaptation followed by the data pattern once (no rmal or single wake up) or twice (double wake up) to be identified. we recommend a transmission protocol as shown on figure 15 and figure 16 . the preamble consists of a half-bit pattern 1010 ... with a specified number n pre of half-bits (n pre must be an even number in order to get complete 1/0 pairs). n pre depends on the application and has influence on the wakeup and overload sensitivity. we recommend a minimum of n pre = 8 half-bits (according to 4 manchester bits ?1?). figure 15. wake up frame of as3931 with single wake data pattern figure 16. wake up frame of as3931 with double wake data pattern preamble n pre half - bits data 96 5.86 ms (16 half - bits) wake lf carrier amplitude preamble n pre half -bits data 96 5.86 ms (16 half -bits) wake lf carrier amplitude data 96 5.86 ms (16 half - bits) ams ag technical content still valid
www.austriamicrosystems.com/as3931 revision 6.2 16 - 30 as3931 datasheet - detailed description 8.3.2 wake up detection a wake signal is generated if and only if all 8 logic 1 half-bits and a predefined number of logic 0 half-bits have been identi fied as correct. the wakeup detection criteria can be changed: the number of invalid zero half-bits can be programmed from 0 to 3. a valid wake up frame can be detected at only one of the 3 channels or at more then one channel simultaneously. the single wake signals of each channel are ored together to a common wake signal figure 13 . in case of using the double wake up feature, the settings of the allowed zero half-bit errors apply for each of the sent data p a ttern ind ividually. e.g. if you configure the as3931 to allow 2 zero half-bit errors, the first data pattern can contain up to two invalid zero hal f-bits as well as the second data pattern, but it is not possible that the first pattern contains 3 and the second data pattern contains one zero hal f-bit error (what in total would give the same number of allowed zero half-bit errors as before). note that a double-wake-pattern detection is possi ble also if the two consecutive single-wake-patterns are assigned to different channels: e.g. if the first pattern is recognized at channel 2 and t he second pattern is recognized at channel 3, then a double-wake-pattern is recognized and the wake pin is activated. all c hannel combinat ions are p ossible. in case of different channels, it is not possible to decide which channel received the first and which channel received the second data pattern. 8.3.3 wake signal clearing after a wake up detection, the wake output signal must be reset via the serial programming interface. this is done by toggling the bit c5 in the channel select register from low to high and vice versa. this is valid for both cases the single wake pattern and the double wa ke pattern detection. furthermore, it is also valid for an internal generated artificial wakeup (see extended operation on page 24) . 8.3.4 wake signal after por after a power on reset (por), the wake signa l is activated (low). therefore, after startup the wake signal must be cleared as i f a valid wake up would have been detected. 8.3.5 rssi operation the rssi signal of a selected channel can be measured at the rssi pin. each channel can be selected by register settings. to ca librate the rssi measurement, the lf inputs can be shortcutted with approximately 500 by internal register settings. doing so, the rssi voltage offset can b e measured. the rssi ? signal is buffered at the rssi pin. the buffer can be deactivated by register settings; in this cas e the rssi pin is tristated (high impedance). however, if the cs signal is not activated, the rssi pin is tristated. this has to be kept in mind when programming the as3931 via the serial programming interface (the cs signal is used to latch the serial data into the selected register at t he falling edge of cs). 8.4 serial programming interface timing figure 17. spi timing waveforms scl sda cs a0 a1 d4 d5 tdvch tclk tch tcl tshch tchsl tsl tchdi ams ag technical content still valid
www.austriamicrosystems.com/as3931 revision 6.2 17 - 30 as3931 datasheet - detailed description 8.5 input signal w aveform definition figure 18. input signal waveform vin 0.9*vin 0.1*vin t rise t fall ams ag technical content still valid
www.austriamicrosystems.com/as3931 revision 6.2 18 - 30 as3931 datasheet - configuring the product 9 configuring the product 9.1 serial programming interface the as3931 is programmed via an unidirectional three wire serial programming interface.the 3 lines are: cs: chip select, used for selecting as3931 and for data latching scl: serial clock sda: serial data a block of 8 bit data starting with the lsb is sent according to the diagram shown in fi gure 19 . the received block of 8 bit data is shifted into an 8 bit latch. the two lsbs are register address bits and the remaining 6 bits are data bits. the register address bits a1 and a0 are dec oded and the 6 data bits are stored into one of three 6 bit registers with the falling edge of cs. figure 19. protocol of 8 bit data serial transmission 9.2 power on register table 4. register data bit por state description p0 1 enable channel 1 p1 1 e nable channel 2 p2 1 enable channel 3 p3 1 enable regulator p4 0 antenna rotator bit 1 p5 0 antenna rotator bit 2 table 5. register address bit value a0 0 a1 0 cs sda address data a0 a1 d0 d1 d2 d3 d4 d5 d = t : test mode register scl d = p : power on register d = c : channel select register d = m: correlator mode register ams ag technical content still valid
www.austriamicrosystems.com/as3931 revision 6.2 19 - 30 as3931 datasheet - configuring the product 9.2.1 p0, p1, p2 (channel enable) if the bit p0, p1 or p2 is set to 1, the related channel is enabled. that means, the logarithmic envelope amplifier and the cor relator are enabled and ready to receive a wake up frame. when disabled, the channel is off, taking no current except for the bias cell to the ampl ifier. after a power on, all channels are enabled. note: shad ed cells show por-states 9.2.2 p3 (regulator enable) bit p3 enables the regulator (vreg 2.4 v) or switches off the regulator (vreg = vcc). if the regulator is switched off, then th e voltage at pin vcc is bypassed unregulated to the internal circuits. after a power on, the regulator is on. 9.2.3 p4, p5 (antenna rotator/input shortcut) bits p4 and p5 are used to set the antenna connection mode or to shortcut the differential inputs of each amplifier. see table 28 for the description of the rotator modes. 9.3 rssi channel select register table 6. p0, p1, p2 bit mode p0, p1, p2 mode 0 channel disabled 1 channel enabled table 7. p3 bit mode p3 mode 0 regulator disabled 1 regulator enabled table 8. p4, p5 bit mode p4 p5 mode 0 0 connection mode1 1 0 connection mode2 0 1 connection mode3 1 1 amplifier inputs shorted table 9. antenna rotation modes connection mode1 connection mode2 connection mode3 antenna 1 channe l 1 antenna 2 channel 1 antenna 3 channel 1 antenna 2 channel 2 antenna 3 channel 2 antenna 1 channel 2 antenna 3 channel 3 antenna 1 channel 3 antenna 2 channel 3 table 10. register data bit por state description c0 0 rssi select bit 1 c1 0 r ssi select bit 2 c2 0 rssi output mode bit 1 c3 0 rssi output mode bit 2 c4 0 channel attenuator c5 0 wake clear ams ag technical content still valid
www.austriamicrosystems.com/as3931 revision 6.2 20 - 30 as3931 datasheet - configuring the product 9.3.1 c0, c1 (rssi channel select) bits c0 and c1 are used to select the channel whose rssi signal is multiplexed to the rssi pin. in case of both bits c0 and c1 set to 1, a bandgap voltage vbg (1.25 v) appears at the rssi pin. after power on, channel 1 is selected. 9.3.2 c2, c3 (rssi output mode) bits c2 and c3 define the rssi pin function. note: the rssi pin function also depends on the signal cs. if cs = 0, the rssi pin is always in the high impedance state. this is als o t he case after power on. the wake or single wake function is sele ct ed together with bits t0 ? t2 and c0 ? c1. for more information see extended operation on page 24 9.3.3 c4 (channel attenuator) when bit c4 is set, a resistor (app. 1.5 k ) is connected across the differential inputs of each channel. this resistor reduces the q-factor of the antenna resonant circuit; therefore the received signal is reduced too. the amount of damping depends on the q-factor of the an tenna circuit. table 11. register address bit value a0 1 a1 0 table 12. c0, c1 bit mode c0 c1 mode 0 0 channel 1 1 0 channel 2 0 1 channel 3 1 1 vbg (t0=0), wake (t0=1) table 13. c2, c3 bit mode c2 c3 rssi pin function 0 0 high z 10 analog output: rssi of selected channel or vbg 01 digital output: wake, single wake or data 1 1 not used table 14. c4 bit mode c4 mode 0 input attenuators disabled 1 input attenuators enabled ams ag technical content still valid
www.austriamicrosystems.com/as3931 revision 6.2 21 - 30 as3931 datasheet - configuring the product 9.3.4 c5 (wake clear) bit c5 is used to reset the active low wake pin after the pin has been set as a re sult of receiving a valid code word (single o r double wake pattern) by one of the 3 channels, a por or an internally generated wakeup. setting bit c5 to 1, the wake pin is reset to high and held in high state, to enable the channels for the next wake up signal, the bit c5 must be toggled to 0 afterwards. after power on, the wake-pin is activated and the bit c5 has to be toggled high and low after a power on. 9.4 test mode register 9.4.1 t0 (test mode enable) bit t0 is used to define the pin function of the wake pin. when bit t0 is reset to 0, the wake pin is used for normal wake up d etection (single or double wakeup from the receiver channels or internally generated wakeup). when bit t0 is set to 1, testmode signals are mult iplexed to the wake pin according to the selected test mode (t1, t2). after power on, the normal wake up detection mode is selected. 9.4.2 t1, t2 (test mode select) when bit t0 is set to 1, the following signals can be mapped to the wake pin. for signal description (see figure 13) . data: received bit stream of the selected channel wake: detected wake up of the selected channel for the data and wake signal select the des ired channel by setting bits c0 and c1. table 15. c5 bit mode c5 mode 0 no effect 1 wake=h table 16. register data bit por state description t0 0 test mode enable t1 0 t est mode select bit 1 t2 0 test mode select bit 2 t3 0 not used t4 1 rssi step t5 0 wake generator on/off table 17. register address bit value a0 0 a1 1 table 18. t0 bit mode t0 wake pin function 0 wake 1 test mode signals table 19. t1, t2 bit mode t1 t2 wake pin function 0 0 data of selected channel 1 0 wake of selected channel ams ag technical content still valid
www.austriamicrosystems.com/as3931 revision 6.2 22 - 30 as3931 datasheet - configuring the product 9.4.3 t3 not used; must always be programmed to 0 by the user! 9.4.4 t4 (rssi step select) bit t4 is used to switch between a high and a low rssi step. for more information on rssi steps see extended operation on page 24 . 9.4.5 t5 (wake generator on/off) bit t5 is used to activate the wake generator. if activated, an artificial parasitic wakeup is generated every 2 hours. 9.5 correlator mode register 0 1 not used 1 1 not used table 20. t4 bit mode t4 mode 0l o w r s s i s t e p 1 high rssi step table 21. t5 bit mode t5 mode 0 wake generator off 1 wake generator on table 22. register data bit por state description m0 0 correlator off m1 0 single/double wake pattern m2 0 zero-bit detection mode bit1 m3 1 zero-bit detection mode bit2 m4 1 detector threshold select m5 0 not used table 23. register address bit value a0 1 a1 1 table 19. t1, t2 bit mode t1 t2 wake pin function ams ag technical content still valid
www.austriamicrosystems.com/as3931 revision 6.2 23 - 30 as3931 datasheet - configuring the product 9.5.1 m0 (correlator off) bit m0 is used to simultaneously turn off all 3 correlators. this is done by turning off the correlator clocks. this can be use d to reduce power consumption when the direct data mode is used. 9.5.2 m1 (single/double wake pattern) bit m1 selects the number of data patterns that are necessary for wakeup detection. 9.5.3 m2, m3 (zero-half-bit detection mode) bits m2 and m3 select the number of zero-half-bits that are allowed to be invalid. a high level of allowed invalid zero-half-bi ts increases the error tolerance related to noise or interference?s, that means that the probability for the detection of a valid wake pattern increas es. note that in turn the immunity against parasitic wakeups (wake detection when no data has been sent, due to noise or interference?s) is reduced. 9.5.4 m4 (detector time constant) bit m4 is used to switch between a large and a small of the detector threshold adoption filter. a large is recommended, because it increases the noise margin. a small can be used to improve the wake sensitivity when non-specified wake-patterns are used. 9.5.5 m5 not used; must always be programmed to 0 by the user! table 24. m0 bit mode m0 mode 0l o w r s s i s t e p 1 high rssi step table 25. m1 bit mode m1 mode 0 single data pattern 1 double data pattern table 26. m2, m3 bit mode m2 m3 wake pin function 0 0 3 invalid zero-bits allowed 1 0 2 invalid zero-bits allowed 0 1 1 invalid zero-bits allowed 1 1 0 invalid zero-bits allowed table 27. m4 bit mode m4 mode 0 small 1 large ams ag technical content still valid
www.austriamicrosystems.com/as3931 revision 6.2 24 - 30 as3931 datasheet - extended operation 10 extended operation 10.1 power management 10.1.1 sleep mode in sleep mode, all channels are switched off, taking no current except for the bias cells of the amplifiers. sleep mode is ente red by register setting, bits p0, p1, p2 set to 0. the remaining elements that take current are the oscillator and the regulator (if used). the serial programming interface remains active also in the sleep mode. 10.1.2 standby mode in standby mode, selected channels are switched on, ready to receive data. the amplifier of the selected channel is on, whereas the correlator is powered down as long as no input signal is detected at the input. enabling the related channel when setting bits p0, p1 or p3 e nters the standby mode. in the standby mode, the current consumption increases by the amplifier currents compared to the sleep mode. 10.1.3 receive mode an enabled channel automatically changes from the standby mode to the receive mode as soon as an input signal is detected. the channel stays in receive mode as long as an input signal is detected. in receive mode, the correlator of the channel is active, scannin g the input signal waveform for a valid wake up pattern. the channel goes back to standby mode if no input signal is detected for more then a fixe d timeout period. the timeout period is approximately 3.3 ms. by this operating principle it is guaranteed, that the correlators are only active and taking current as long as it is really necessary. 10.1.4 regulator on/off the regulator can be switched off to reduce the current consumption. when switching off, the supply voltage is bypassed unregulated to the internal circuits, so vreg = vcc. otherwise, the internal voltage is regulated to 2.4 v. switching off the regulator saves abou t 1 a of current. the regulator should only be switched off, when vcc is not higher then 3.3 v, otherwise the current consumption is increased be cause the internal circuits will then take more current. 10.1.5 typical current consumption in different modes the table 28 gives an overview of the typical current consumptions in the different modes. all three channels are used in this case. power consumption of course can be further reduced when not all three channels are enabled. 10.1.6 rssi step the rssi step is defined as the change in the rssi signal voltage if the input amplitude steps from zero to a defined (small) v alue. for example when changing the input signal amplitude from zero to 1 mvpp, the rssi signal makes a step of app. 175 mv if the bit t4 is set to 1 (compare to figure 8 on page 21). if not needed, this step can be reduced to a lower value (t4 = 0), which decreases the current consumptio n of each channel by app. 120 na. 10.1.7 antenna rotation the 3 possible input signals can be distributed to the 3 channels in 3 different connection modes. using this feature, the diff erences between the individual antenna voltages and also the differences of the individual rssi-voltages of the channels can be handled. for exampl e to eliminate the differences of the rssi-voltages it is possible to use only one channel and to multiplex it to each antenna. the bits p4 an d p5 select the antenna rotation modes. 10.2 input attenuation a nd input shortcutting all differential lf-inputs are each shorted by approximately 500 when setting bits p4 and p5 both to 1. this can be used to measure the rssi-voltage with no input signal present; therefore the rssi offset can be calibrated. it should be taken into account that th e shortcut resistance can not be made zero due to design restrictions, so the input signal cancellation is not 100% (depending on the ante nna circuit). table 28. typical current consumption operating mode regulator on, vcc = 3 v regulator off, vcc = 2.4 v sleep 0.8 a 0.3 a st andby 7.0 a 6.5 a receive 7.2 a 6.8 a standby & rssi low step 6.6 a 6.1 a ams ag technical content still valid
www.austriamicrosystems.com/as3931 revision 6.2 25 - 30 as3931 datasheet - extended operation similar to the input shortcutting option, a 1.5 k resistor can be connected across the differential inputs when setting bit c4 to 1. this input attenuation allows handling of very strong input signals by damping the antenna circuit. the damping depends on the q-factor of the receiver circuits. 10.3 wake signal at the rssi pin the wake signal, which is normally available at the wake pin, can be mapped to the rssi pin additionally, which then becomes a digital output. to do this, set the following bits: c3 = 1 and c2 = 0 in the channel select register (rssi output mode digital) c0 = 1 and c1 = 1 in the channel select register note: the rssi pin is only active if the cs signal is active (cs = 1), otherwise rssi is high z. 10.4 single wake operation the single wake signals of each channel can be mapped to the wake pin. normally, the 3 wake signals are ?ored? together and map ped to the wake pin, so the channel with the str ongest input signal wi ll generate a wake signal. to map a single wake signal to the wake pin, follow the steps: 1. enable test mode: set t0 = 1 in test mode register 2. select test mode: set t1 = 1 and t2 = 0 in test mode register 3. select channel: set c0 and c1 in the channel select register the single wake signals can also be mapped to the rssi pin, which then becomes a digita l output pin. to do this, make this step : ? select rssi output mode digital:set c2 = 0 and c3 = 1 in the channel select register the rssi pin is only active if the cs signal is active (cs = 1), otherwise rssi is high z. it is possible to operate the wake pin in the normal mode first (that is all three single wake signals ored together) and after a wake up detection, to use the single wake mode to check which channel received the wake pattern. this must be done before clearing the wake pin. it is also possible to ope rate the wake pin in normal wake mode and simultaneously to operate the rssi-pin in single wake mode. 10.5 using the wake generator the wake generator generates artificial parasitic wakeup?s every 2 hours as a time base for an external-controlling unit to ide ntify situations where no true wakeup?s can be detected for a long time. for this purpose the external controlling unit must be able to distingu ish between a true wakeup (generated by one of the receiving channels) or an artificial wakeup. this is done by checking the receiving channels us ing the single wake operation (see single wake op eration on page 25) . if a wakeup has occurred and no one of the receiving channels can be identified as the trigger for the wake up, then the wake generator has trigger ed th e wakeup. in this case, the wake signal has to be cleared as if a receiving channel would have triggered the wake up. note: the internal counter, that generates the internal wakeup by an overflow, can not be reset by clearing the wake pin or other act ions. the time between two artificial wakeups is approximately 2 hours (2h 16min 32sec); however, the first artificial wakeup generat ed b y the wake generator after activation of the feature (by setting bit t5 = 1) ma y come earlier then in 2:16:32 hours. this time is not defi ned. after the first artificial wakeup, the time between two wake ups is then 2 hours. the wake generator must be activated by programming the bit t5 = 1 in the test mode register. ams ag technical content still valid
www.austriamicrosystems.com/as3931 revision 6.2 26 - 30 as3931 datasheet - extended operation 10.6 direct data mode in direct data mode, the received data of a selected channel can be mapped to the wake pin. the data signal is the digital outp ut of the detector and is normally fed to the correlator, where it is scanned for th e wake pattern (see figure 13) . to get the data signal at the wake pin, follow the steps: 1. enable test mode: set t0 = 1 in test mode register 2. select test mode: set t1 = 0 and t2 = 0 in test mode register 3. select channel: set c0 and c1 in the channel select register the direct data signals can also be mapped to the rssi pin, which then becomes a digital output pin. to do this, make this step : select rssi output mode digital:set c2 = 0 and c3 = 1 in the channel select register note: the rssi pin is only active if the cs signal is active (cs = 1), otherwise rssi is high z. 10.7 correlator modes operation of the correlators can be modified regarding the error tolerances for the zero-half-bits. in this case, the number of zero-half-bits that is allowed to be invalid can be set from 0 to 2. please take into account that an increased error tolerance also reduces the im munity against parasitic wakeups (wake det ection when no data ha s been sent, due to noise or interferences). 10.8 threshold adaptation filter time constant bit m4 is used to switch between a large and a small w of the detector threshold adaptation filter. a large w is recommended, because it increases the noise margin. a small w can be used to improve the wake sensitivity when non-specified wake-patterns are used. 10.9 rssi and wake pin modes this table gives an overview of the diff erent signals that can be mapped to the rssi and wake pin and how to program it. table 29. rssi/wake-pin modes bit/pin chip select pin rssi output mode 2 rssi output mode 1 channel select 2 channel select 1 wake test mode enable test mode select 2 test mode select 1 mode cs c3 c2 c1 c0 t0 t2 t1 wake-pin: wake x x x x x 0 x x w ake-pin: data1 x x x 0 0 1 0 0 wake-pin: data2 x x x 0 1 1 0 0 wake-pin: data3 x x x 1 0 1 0 0 wake-pin: wake1 x x x 0 0 1 0 1 wake-pin: wake2 x x x 0 1 1 0 1 wake-pin: wake3 x x x 1 0 1 0 1 rssi-pin: wake 1 1 0 1 1 x x x rssi-pin: data1 1 1 0 0 0 x 0 0 rssi-pin: data2 1 1 0 0 1 x 0 0 rssi-pin: data3 1 1 0 1 0 x 0 0 rssi-pin: wake1 1 1 0 0 0 x 0 1 rssi-pin: wake2 1 1 0 0 1 x 0 1 rssi-pin: wake3 1 1 0 1 0 x 0 1 ams ag technical content still valid
www.austriamicrosystems.com/as3931 revision 6.2 27 - 30 as3931 datasheet - package drawings and markings 11 package drawings and markings the product is available in 16-pin tssop package. figure 20. 16-pin tssop package marking: yywwmzz. yy ww m zz year (i.e. 10 for 2010) manufacturing week assembly plant identifier assembly traceability code symbol min nom max a- -1.20 a1 0.05 - 0.15 a2 0.80 1.00 1.05 b0.19 - 0.30 c0.09 - 0.20 d 4.905.005.10 e - 6.40 bsc - e1 4.30 4.40 4.50 e - 0.65 bsc - l 0.450.600.75 l1 - 1.00 ref - symbol min nom max r0.09 - - r1 0.09 - - s0.20 - - 10o 8o 2-12 ref- 3-12 ref- aaa - 0.10 - bbb - 0.10 - ccc - 0.05 - ddd - 0.20 - n1 6 as3931 yywwmzz notes: 1. dimensioning & tolerancing conform to asme y14.5m-1994 . 2. all dimensions are in millimeters. angles are in degrees. ams ag technical content still valid
www.austriamicrosystems.com/as3931 revision 6.2 28 - 30 as3931 datasheet - revision history revision history table 30. revision history revision date owner description 6.1 apr 22, 2010 dhe changed to new template updated the ordering table table 31 6.2 apr 14, 2011 updated absolute maximum ratings, package drawings and markings. ams ag technical content still valid
www.austriamicrosystems.com/as3931 revision 6.2 29 - 30 as3931 datasheet - ordering information 12 ordering information where: t = temperature range z= others p= package type ts = tssop d = delivery form: u= tubes t = tape & reel note: all products are rohs compliant and pb-free. buy our products or get free samples online at icdirect: http ://www.austriamicr osystems.com/icdirect for further information and requests, please contact us m ailto:sales@austriamicrosystems.com or find your local distributor at http://www.austriamicros ystems.co m/distributor table 31. ordering information device id part number description delivery form 1 1. dry pack sensitivity level = 3, according to ipc/jedec j-std-033a package AS3931-TPD as3931-ztsu tubes 16-pin tssop as3931-ztst tape and reel 16-pin tssop ams ag technical content still valid
www.austriamicrosystems.com/as3931 revision 6.2 30 - 30 as3931 datasheet - copyrights copyrights copyright ? 1997-2011, austriamicrosystems ag, tobelbaderstrasse 30, 8141 unterpremstaetten, austria-europe. trademarks registe red ?. all rights reserved. the material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective companies. disclaimer devices sold by austriamicrosystems ag are covered by the warranty and patent indemnification provisions appearing in its term of sale. austriamicrosystems ag makes no warranty, express, statutory, implied, or by description regarding the information set forth he rein or regarding the freedom of the described devices from patent infringement. austriamicrosystems ag reserves the right to change specificatio ns and prices at any time and without notice. therefore, prior to designing this product into a system, it is necessary to check with austriamic rosystems ag for current information. this product is intended for use in normal commercial applications. applications requiring extended temper ature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems ag for each application. for shipments of les s than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. the information furnished here by austriamicrosystems ag is believed to be correct and accurate. however, austriamicrosystems ag shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. no obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems ag rendering of technical or other services. contact information headquarters austriamicrosystems ag tobelbaderstrasse 30 a-8141 unterpremstaetten, austria tel: +43 (0) 3136 500 0 fax: +43 (0) 3136 525 01 for sales offices, distributors and representatives, please visit: http://www.austriamicrosystems.com/contact ams ag technical content still valid

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